Electronic chip designers develop chips of ever increasing complexity using more and more transistors. Complex chips are often called a Systems-on-a-chip (SOC). SOC designers frequently simplify the development task by incorporating intellectual property (IP) modules into their design. IP modules implement pre-defined functions, are often developed by third parties and have usually been successfully used in multiple, earlier designs.
IP module developers make their modules configurable so that the module can be used in as many designs as possible. Configuration options affect the functionality of the module and how it is implemented. IP modules are usually written in RTL design languages such Verilog and VHDL. The SOC designer can customize an IP module by defining parameter values and specifying macro keyword values. Different members of the SOC development team may use different configuration options. Team members who emulate the design using FPGAs may use configuration options that allow the design to be implemented on an FPGA. Team members concerned with speed, timing and power may use different configuration options.
For many designs the SOC designer has to make significant modifications to IP modules. IP modules typically use generic memories and have few or no options for limiting power use. The SOC designer may replace all generic memories defined in the IP module with memory modules customized for the target process. The SOC designer may wish to replace time-critical or power-inefficient RTL constructs. The SOC designer wants to preserve the configurability of the IP module as he or she modifies it. Modifying these configurable IP modules is often a difficult, error-prone and time-consuming task. Each modification needs to work with all possible configurations. The problem is often compounded because the IP module developers are typically improving their IP modules and supplying periodic updates. If the SOC designer wants to use the latest version of an IP module, he or she will have re-make all of his or her changes.
Existing design tools treat RTL macros as pre-processing directives. They simplify the RTL by propagating macro values and effectively remove all reference to the macros.
SOC designers need an electronic design tool to help them modify configurable modules and SOC designs.